The function of modern electronic systems that are intended to be implemented as integrated circuits is often expressed in a Hardware Description Language (HDL). The purpose of the HDL is to provide a high productivity design media for designers to express the functionality of the system in an unambiguous form, which can then be simulated to verify the correctness of the design before reducing the design into hardware. Various techniques exist today to convert such HDL descriptions into an actual hardware implementation.
Conventional approaches to realize hardware implementation of a HDL description are:
1. Custom Application Specific Integrated Circuit (ASIC)
Major custom ASIC implementation steps comprise: 1.) Synthesizing the HDL into a lower level description (e.g., a gate level netlist) that can be mapped into hardware logic functional blocks; 2.) Placing the logic function blocks to minimize routing delay between them; 3.) Creating the routing to interconnect blocks; 4.) Verifying the functionality, timing, power consumption, and signal integrity of the design using Electronic Design Automation (EDA) software tools; 5.) Creating a mask set for an ASIC or multiple ASICs; and 5.) Fabricating the chip.
The advantages of ASIC implementation are: high performance, small die size (low cost), and low power consumption, at the expense of high nonrecurring engineering (NRE) cost, high risk, and long design time.
2. Field Programmable Gate Array (FPGA)
FPGAs are programmable devices in which the device function is defined by the program downloaded (as a bit stream) into an on-board storage. An FPGA is made up of programmable logic function blocks and programmable wires for connecting functional blocks.
Similarly to the custom ASIC approach, the HDL description is synthesized into logic function blocks already built into the base array of the FPGA. The FPGA design software creates a bit stream used to configure the programmable function blocks and wires to perform the specific function required by the design.
Unlike the ASIC approach, no custom physical implementation is required in the FPGA approach. The FPGA approach offers fast turn around and low design cost and risk, but at the expense of higher device cost, lower performance, and higher power consumption than custom ASICs.
ASICs and FPGAs are direct hardware mapping approaches in which the logic function contained in the HDL description is implemented directly by corresponding logic gates in the underlying hardware. An alternate approach to the direct mapping technique is the so-called processor-based logic evaluation approach (e.g. accelerators or emulators).
In the processor-based approach, logic values are computed using clusters of “processors”. While the literature refers to the computing elements as processors, they are actually primitive computing elements to which a single command can be dispatched. In response to the command and corresponding operands, if any, the primitive computing element returns a result. For example, logic computing elements such as AND, OR, shift, etc. are implemented. Adder computing elements that add or subtract operands are sometimes implemented. In some cases, the “processors” may be of the complexity of a 4-input function look-up table. However, the “processors” are not processors in the general purpose processor sense, and do not independently execute programs. The HDL description is compiled into an instruction stream which routes data from memory to and from various processors for evaluation. Simple “processors” create complex interconnect (heavy data traffic) requirements and long execution time because complex logic functions require multiple processors and multiple clock cycles to execute.
Prior attempts to apply complex (e.g. general purpose) processors have been problematic due to the fact that the HDL description has always been synthesized into low level primitive logic functions. For example, in the conventional “processor”-based approach the compiler decomposes the HDL description into a collection of primitive logic operations and then schedules the execution of these operations by various “processors”. The results of each primitive operation often need to be stored and then retrieved later to be use as the input operand of subsequent logic evaluation. The heavy data traffic in the conventional “processor”-based approach is the Achilles' heel of performance and power consumption.
There has been no effective technique to map primitive logic functions into the complex instruction set of a general purpose processor. As a result, processor-based logic evaluation techniques often employ simple “processors”, seldom meet the performance, power consumption or cost requirements of the system, and are not a viable alternative to ASICs or FPGAs to realize the design. Therefore, the processor-based approach has been relegated to a logic evaluation technique mostly used in logic emulation and simulation acceleration systems to verify the HDL before hardware implementation in a custom ASIC. This is because lower speed, higher power consumption, and higher cost are less critical in such systems in return for faster turn around.